The present invention relates generally to computer processor architecture, and more specifically, to a heterogeneous core microarchitecture for a computer processor.
As multi-core processors become more commonplace, power management issues become more important. In a design era in which “green computing” is of ever-increasing importance, system- or datacenter-level power management and control, requires effective, programmable power management accessibility across computing elements within each microprocessor chip. In addition to providing large, efficient power reduction capability via dynamic voltage and frequency control, there is a need to provide smaller degrees of power reduction (when needed) at minimal complexity and performance overhead. The current generation of multi-core microprocessor chips does not provide such fine-grain, global, multi-core power management accessibility.
Power management solutions may incorporate particular power-saving mechanisms for a given core or non-core component within a microprocessor chip. However, local conditions, such as temperature or region-specific workload variations, trigger individual power-saving mechanisms and are not amenable to effective global control and optimization via an on- or off-chip system power manager.